Canon Solutions For Advanced Heterogeneous Integration
Canon Solutions for Advanced Heterogeneous Integration and Fan-Out ProcessesDoug Shelton1, Ken-Ichiro Mori2, Yoshio Goto2, Hiromi Suda2Industrial Products Division, Canon U.S.A., Inc., San Jose, USA2Semiconductor Production Equipment PLM Center 1, Canon Inc., Utsunomiya, nce Computing systems can employ leadingedge Heterogeneous Integration (HI) technology includingFan-Out Wafer Level Packaging (FOWLP) and high-densityRedistribution Layers (RDL) to maximize systembandwidth and performance.These More-than-Moorestrategies are growing in importance and present uniquechallenges that must be overcome to enable mainstreamadoption.FOWLP roadmaps for interconnections between SoC(System on Chip) and DRAM (Dynamic Random AccessMemory), split-die FPGA (Field-Programmable Gate Array)and image sensors and SoC are driving RDL scaling andaggressive FOWLP processes are targeting 0.8 µm designrules. High-resolution lithography is required for highdensity, fine-RDL applications and the main lithographychallenge is to provide a large Depth-of-Focus (DoF) toreliably pattern sub-micron RDL traces across a largeexposure field.This paper details an analysis of candidate opticalconditions for sub-micron imaging including datademonstrating the DoF performance of an optimizedlithography system (stepper). To meet the high-resolutionrequirements of fine-RDL processes, Canon developed theFPA-5520iV-HR [20iV-HR] i-line stepper that employs anew projection optical system featuring a maximum 0.24Numerical Aperture (NA) and a 52 x 34 mm field size. Wewill present data illustrating that 0.24 NA steppers canprovide excellent resolution and pattern fidelity throughouteach exposure field across the entire wafer.High-density FOWLP wafers can also display extreme dieshift, warpage and topography that must be addressed toenable high-yield and high-productivity processes.Die placement error in FOWLP wafers creates orders ofmagnitude more alignment error versus traditional siliconwafers and advanced alignment compensation is required toimprove overlay matching.Alignment solutions forprocessing distorted FOWLP wafers include the Grid-PAsystem that automatically corrects the wafer loadingposition based on die-grid sampling, and EnhancedAdvanced Global Alignment (EAGA) that allows thestepper to measure and compensate for shift, rotation andintra-field magnification errors on a die-by-die basis.FOWLP reconstituted wafers can also experience largewarpage that can decrease productivity and DoF and tocombat these challenges, our steppers have been designed tohandle wafers with over 5 mm of warpage and are alsobased on a Front-End-Of-the-Line (FEOL) stepper platformthat offers die-by-die tilt and focus measurement andcompensation to maximize focus accuracy and DoF.This paper provides an analysis of key lithographychallenges facing aggressive FOWLP and fine-RDLprocesses details of stepper technology that helps enablehigh-density integration in mass-production. We remaincommitted to enabling innovation through lithographysystem performance upgrades and development of originaloptions supporting current and future FOWLP and fineRDL processes.Keywords: Fan-Out Wafer Level Packaging, Fan-Out PanelLevel Packaging, High-Bandwidth Memory, lithography,Heterogeneous IntegrationINTRODUCTIONHigh-Performance Computing systems can employ leadingedge Heterogeneous Integration (HI) technology includingFan-Out Wafer Level Packaging (FOWLP) and high-densityRedistribution Layers (RDL) to maximize systembandwidth and performance [1]. These More-than-Moorestrategies are growing in importance and offer uniquechallenges that must be overcome to enable mainstreamadoptio requiring high-yield; low-cost processes.Key lithography process requirements for 3D and 2.5DMore-than-Moore applications are provided in Figure 1 andinclude accurate processing of severely warped anddistorted bonded wafer stacks and reconstituted wafers. .Figure 1: Key lithography process requirementsfor 3D and 2.5D applicationsOriginally published in the proceedings of the International Wafer-Level Packaging Conference, San Jose, California on October 22-24, 2019
More-than-Moore strategies have been a hot topic for morethan a decade, starting with 3D integration using ThroughSilicon Vias (TSVs) and evolving into today’s promisingtechnology of Heterogeneous Integration using interposersand fine-RDL.Resolution 0.24 NA Option can provide stable 0.8 µmimaging across throughout the entire exposure area.Because advanced GPUs and FPGAs used in autonomousdriving require wideband interconnection with memories,RDL layers in next generation interposers will require submicron patterning [2] as is illustrated in Table 1.Table 1: Comparison of die-size, bandwidth and RDLsize requirement for high-bandwidth memoryLithography process optimization plays a role in reducingcosts as uniform imaging performance is required to fullyexploit the benefits of HI, FOWLP and Fan-Out Panel LevelPackaging (FOPLP). we previously reported lithographychallenges for with aggressive processes[3], and Table 2includes an updated list of challenges including demands forhigh-resolution lithography and accurate overlaycompensation to increase interconnect density andultimately electronic system bandwidth,Updateshighlighted in bold will be reviewed in detail in this paper.Figure 2: Canon Stepper IllustrationTable 2: HeterogeneousChallengesRDL scaling is a key requirement to enable multi-chipinterconnection market expansion using FOWLP orinterposers. Advanced packaging roadmaps already require1.0 µm RDL for interconnecting SoC and DRAM, SoC andimage sensors and split-die FPGA with future applicationstarget 0.8 µm utions 1 micron resolution0.24 NA LensVertical thick resist patterningLarge DOF lensLarge topographyMulti-channel optical Auto-FocusWafer Warpage 5 mmWaferYield / ProductivityWafer Edge Shield(WES)ProcessingWafer Edge Exposure(WEE)AlignmentBack-side alignment“TSA-Scope” with IRFlexibilityMark deteriorationNew alignment markGrid Pre-AlignmentOverlayDie grid errorGlobal alignmentAccuracyDie-by-die alignmentTo meet this demand, we have developed steppers that cannow provide new projection optics offering a 0.24Numerical Aperture (NA) and a large 52 x 34 mm exposurefield. 20iV steppers (Figure 2) equipped with the High-This paper reports on a study of photolithographychallenges related to patterning of sub-micron RDL forchip-to-chip wide bandwidth interconnections. We will alsoprovide details optional systems available for the steppersthat can help enable aggressive advanced edPackagingProcessA key lithography challenge for fine-RDL is providing asufficient Depth of Focus (DoF) to accurately resolve submicron features. Front-End-of-Line (FEOL) lithographytools feature large NA optical systems that do not provideenough DoF to resolve sub-micron patterns over largeinterposer topography. On the other hand, traditional BackEnd-of-Line (BEOL) lithography tools struggle to resolvevery fine patterning due to their extremely low NA andleveling systems that can’t reliably position wafers in tightDoF range during exposure.We have a unique position in the lithography tool market. Inaddition to our many years of experience in the FEOLlithography tool business, we have enjoyed strong growth inthe BEOL stepper market since 2011 and we has continuedto develop solutions that add functionality and improveproductivity and yields.Our steppers feature a variable NA (Numerical Aperture)Optical System that can be optimized to improve imagingperformance across a large exposure field. NA directlyaffects imaging performance and it is important to chooseOriginally published in the proceedings of the International Wafer-Level Packaging Conference, San Jose, California on October 22-24, 2019
the optimum NA for each process. Large NA conditionstypically deliver resolution below 1 µm for fine-lineRedistribution Layer (RDL) processes, while the stepperNA can be reduced through recipe parameters to increaseDepth of Focus (DoF) for imaging through thick resists usedfor plating and etch masks.Table 3: i-line Stepper SpecificationsAdvanced Packaging Stepper SpecificationsWafer SizeResolutionFigure 3 shows the relationship between NA and imagingperformance with respect to resolution and DoF. Thesimulation results plot the expected DoF for correspondingresolution targets, for NA values of 0.18, 0.24, 0.37, 0.45and 0.57. The data shows that the largest NA valuesprovide the best overall resolution, although the DoF for a0.8 µm L/S pattern is less than 5 µm which is not ideal. Thesimulations predict that 0.24 NA exposure conditions areoptimum for fine RDL processes, providing the largestprocess window with 7 µm of DoF for 0.8 µm imaging.Because of this background, we have a responsibility tocontribute to fine RDL interposer technology by developinga lithography tool that is optimized for sub-micronprocesses. To meet these requirements, we developed newprojection optics offering 0.24 NA imaging and 52 x34 mmexposure field.NA 300 mm 365 x 306.7 mm (option) 1.5 µm 0.8 µm (option)0.15 - 0.180.24 Max (option)Reduction Ratio2:1Exposure Field52 x 34 mm52 x 68 mm (option)Exposure 365 nm (i-line)Single MachineOverlay AccuracyFront 0.15 µmBack 0.5 µm (option)Wave-Front Engineering In Optics ManufacturingImaging performance and resolution must be maintainedthroughout the entire wafer and within each exposure fieldto maximize process yield. our steppers apply proprietarymanufacturing methods and wave-front engineeringtechnology to minimize lens aberrations that can reduceresolution, while also employing and on-axis optical tiltfocus sensor to compensate for wafer topography on a shotby-shot basis.Resist profiles are affected by lens aberration and it isimportant to control lens aberration for sub-micronresolution. Figure 4 illustrates the relationship betweencoma aberration and pattern size and the simulation showsthat that 0.8 µm pattern resist profiles are sensitive to lensaberration.Figure 3: NA 0.24 is an optimum condition for 0.8 µmimagingNew Projection Optics For Fine-RDL PatterningTo support sub-micron RDL patterning, we developed anew projection optical system and lens that features a largeNA and large exposure field. The new High-Resolution(HR) projection optics are an option offering an 0.24 NAand a 52 x 34 mm exposure field and standard and optionalspecifications are summarized in Table 3.Figure 4: Impact of Coma aberration (simulation)We employs high-precision design and manufacturingtechnology developed over many years of FEOL experiencein wave-front engineering and manufacturing to produce astable, supply of low-aberration lenses capable of achievingsub-micron resolution.Figure 5 provides an outline of the Phase Measurementinterferometer (PMi) system that we use to quickly andaccurately collect lens aberration measurement data. PMiobtains the interference pattern of a reference light wave andOriginally published in the proceedings of the International Wafer-Level Packaging Conference, San Jose, California on October 22-24, 2019
a light wave passed that has passed through the lens toenable high precision lens aberration analysis and highquality lens assembly.Figure 6: NA 0.24 resolution testing demonstrates 8 µm DoF for 0.8 µm Line/Space imagingFigure 7 shows examples of cross-sectional photoresistprofiles for 0.8 µm L/S patterns using 1.48 µm thickTDMR -AR1100 LB (Tokyo Ohka Kyogyo Co. Ltd.) i-linephotoresist. The data shows that 0.24 NA exposure yields alarger 8 µm DoF and is superior to 0.18 NA for 0.8 µmprocesses.Figure 7: 0.24 NA & 0.18 NA imaging results for 0.8 µmLine/Space patternsFigure 5: Outline of Phase Measurement interferometer(PMi) used for aberration analysisResist profile examples 2.5 µm thick i-line photoresist fromJSR are provided in Figure 8. The examples demonstratethat 0.8 µm features patterned using 0.24 NA on a copperseed wafer showed stable resist profiles suitable for highresolution RDL plating processes.Photoresist Patterning StudyKey to lithography performance is the ability to deliverhigh-resolution and high-image fidelity uniformly across alarge exposure field and we have collaborated withphotoresist and electronic materials companies tocharacterize imaging of 0.8 µm features in a variety ofmaterials.Figure 6 demonstrates high-resolution imaging performanceof a 0.24 NA stepper and displays a plot of printed featuresize (Critical Dimension, CD) vs. Focus position for 0.8 µmLine & Space (L/S) patterns. The test was conducted using1.095 µm thick PFi-38 A7 i-line photoresist and a DoFevaluation examined 15 image heights across a 52 x 34 mmfield. Results showed that under an NA 0.24 condition for0.8 µm L/S imaging and given a /- 10% CD budget (- 80nm, 80 nm) yielded a DoF of 8 µm which shouldprovide sufficient focus margin for fine RDL processes.0.80µmFigure 8: 0.8 µm Copper seed layer resist profiles using0.24 NA (2.5 µm thick resist)This data demonstrates that our lithography systems canmeet the fine-RDL imaging requirements to enableaggressive Heterogeneous Integration applications. Thelarge exposure field and high-resolution of the new 0.24 NAHR projection optics can help speed the development oflarge size FOWLP and interposers manufacturing andperformance improvements of FPGA and GPU devices.Die-By-Die Optical Tilt & Focus SystemFOWLP requires RDL layer formation on substrates that arewarped due to molding and material stresses. Waferwarpage can reduce the usable depth of focus in sub-micronRDL processes that have a small focus margin. To helpprovide high-precision focusing across warped wafers, Oursteppers are equipped with an Optical Tilt & Focus (OPTF)Originally published in the proceedings of the International Wafer-Level Packaging Conference, San Jose, California on October 22-24, 2019
System (Figure 9) that enables die-by-de die tilt & focuscompensation.The dioptric lens design also allows steppers to enjoy a 20mm gap between the bottom of the projection lens andwafer surface to help reduce the effects of resist outgassing.Warped Wafer Handling SystemFigure 9: Stepper Optical Tilt Focus SystemThe optical tilt focus system is adapted from FEOL stepperdesigns and offers die-by-die tilt and focus measurementand compensation to maximize focus accuracy and DoF.Prior to exposure of each shot, the optical tilt focus systemprojects multiple beams of LED measurement light ontoeach shot and directs the reflected beams to focus sensors.The focus and tilt position of each shot can be calculatedand compensated in real-time prior to exposure, avoidingpre-exposure topography measurements that can negativelyaffect throughput.FEOL lithography tools have no solutions for warped waferhandling which is a major challenge in packaging processes.BEOL lithography systems must overcome the challenge ofhandling warped wafer and substrates. Our current steppersfeature an advanced wafer handling system that steppers canprocess wafers with more than 5 mm of warpage whichallows processing of reconstituted FOWLP wafers andsilicon interposers that often experience severe warpage anddistortion.In fine pattern exposure, warpage of wafer reduces focusmargin and therefore it is necessary to flatten the warpedwafer prior to exposure. Figure 12 shows wafer flatnessmeasurement of a warped wafer prior to mounting to awafer chuck. Wafer flatness before chucking is 730 µmand after chucking global wafer flatness reduced to 4.3 µmand flatness within a 52 x 34 mm field is reduce to 1.6 µm.Reducing the wafer flatness within each field maximizesDoF and improves process margins.Die-by-die focus compensation in a sample FOWLP waferis shown in Figure 10 with as much as 20 µm chip-to-moldtopography across a wafer. By applying die-by-die focuscompensation, the stepper can reduce the residual focuserror to 10 µm across the wafer (Figure 11) to incresasethe usaable DoF within each field [3].Figure 10: Original FOWLP topography has 20 µmtopography across the waferFigure 12: Global wafer flatness can be reduced from730 µm to 4.3 µm after chuckingDie Rotation Measurement And CompensationOne of the most challenging aspects of FOWLP processeshowever is the requirement to compensate for die-shiftcaused during bonding and molding processes [5].In chip-first processes, large die shift and rotation errors canoccur during the die placement and molding processes.Figure 11: After focus compensation, FOWLPtopography can be reduced to 10 µm across the waferOriginally published in the proceedings of the International Wafer-Level Packaging Conference, San Jose, California on October 22-24, 2019
Wafer notch position is typically defined after molding andposition accuracy is generally poor and not necessarilyrelated to the actual die positions.The typical wafer handling sequence includes a mechanicalpre-alignment step that positions the wafer relative to thenotch before loading to the wafer stage where more accurateoptical alignment steps are performed.It is sometimes difficult to align FOWLP wafers exhibitingpoor notch accuracy which can lower system throughput. Toovercome this issue, we are developing a new Grid Prealignment (Grid PA) function that references the wafernotch and wafer chip layout a to improve pre-alignmentaccuracy. An illustration of the Grid PA alignment systemis provided in Figure 13.LRFor FOWLP wafers exhibiting extreme die-shift, overlay istypically measured and compensated for on a die-by-diebasis during lithography processing to improve overlay andFOWLP process yield. To correct for die-shift errors, oursteppers offer a variety of compensation functions includingthe optional Enhanced Advanced Global Alignment(EAGA) Function to enable die-by-die overlaycompensation to correct for die-shift errors inherent inFOWLP applications.To improve FOWLP overlay, die-by-die alignment (detailedin Figure 15) involves the stepper using its internalalignment system to measure and map out the position ofeach die or field on a wafer prior to exposure. [6]Compensation based on this direct measurement is appliedto the wafer during exposure to improve matching overlayand compensate for die shift errors.X spanFigure 13: Grid-PA System SchematicThe grid prealignment sequence captures a wafer imageusing 2 cameras positioned across the X axis with of thewafer. Grid position measurements (Y position) areperformed on Left (L) and Right (R) positions and thedifference between the L/R Y values are calculated relativeto the span between the cameras. Grid prealignmentcalculates and applies global compensation for chip rotationrelative to the notch reference, making it possible to reduceFOWLP wafer process times as shown in Figure 14 [2]Figure 14: Grid PA reduces mark search and loadingerror correction timesDie-by-Die Overlay CompensationFigure 15 Die-by-die overlay process sequence rement dataDie-by-Die overlay compensation simulations have beenconducted to estimate the effect of applying shot-by-shotcompensation to severely distorted wafers exhibiting largeamounts of wafer and intra-field distortion. A comparison ofconventional linear overlay compensation and Die-by-Dieoverlay performance is shown in Figure 16 The dataillustrates that die-by-die overlay compensation for distortedwafers can reduce overlay error by more than 60% to meetthe accuracy level required for dense sub-micron RDL andTSV fabrication [7].Fine RDL patterns must align and accurately overlay theunderlying die. For non-distorted wafers, steppers typicallyemploy an Advanced Global Alignment (AGA) strategy thatsamples the position of several fields on a wafer, and appliesoverlay compensation to each field based on a linearapproximation based on the sample shot data.Originally published in the proceedings of the International
Canon Solutions for Advanced Heterogeneous Integration and Fan-Out Processes Doug Shelton1, Ken-Ichiro Mori2, Yoshio Goto2, Hiromi Suda2 1Industrial Products Division, Canon U.S.A., Inc., San Jose, USA 2Semiconductor Production Equipment PLM Center 1 , Canon Inc. Utsunomiya, Japan sshelton@cusa.canon.com ABSTRA
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