96FBGA With Lead-Free & Halogen-Free - Samsung Us
Rev. 1.0, Feb. 2016K4B2G1646F2Gb F-die DDR3L SDRAM x1696FBGA with Lead-Free & Halogen-Free(RoHS compliant)datasheetSAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION ANDSPECIFICATIONS WITHOUT NOTICE.Products and specifications discussed herein are for reference purposes only. All information discussedherein is provided on an "AS IS" basis, without warranties of any kind.This document and all information discussed herein remain the sole and exclusive property of SamsungElectronics. No license of any patent, copyright, mask work, trademark or any other intellectual propertyright is granted by one party to the other party under this document, by implication, estoppel or otherwise.Samsung products are not intended for use in life support, critical care, medical, safety equipment, orsimilar applications where product failure could result in loss of life or personal or physical harm, or anymilitary or defense application, or any governmental procurement to which special terms or provisionsmay apply.For updates or additional information about Samsung products, contact your nearest Samsung office.All brand names, trademarks and registered trademarks belong to their respective owners.གྷ 2016 Samsung Electronics Co., Ltd.GG All rights reserved.-1-1.35V
Rev. 1.0datasheetK4B2G1646FDDR3L SDRAMRevision HistoryRevision No.1.0History- First SPEC release-2-Draft DateRemarkEditor16th Feb. 2016-J.Y.Lee
K4B2G1646FdatasheetRev. 1.0DDR3L SDRAMTable Of Contents2Gb F-die DDR3L SDRAM Only x161. Ordering Information .52. Key Features.53. Package pinout/Mechanical Dimension & Addressing.63.1 x16 Package Pinout (Top view) : 96ball FBGA Package . 63.2 FBGA Package Dimension (x16). 74. Input/Output Functional Description.85. DDR3 SDRAM Addressing .96. Absolute Maximum Ratings .106.1 Absolute Maximum DC Ratings. 106.2 DRAM Component Operating Temperature Range . 107. AC & DC Operating Conditions.107.1 Recommended DC operating Conditions . 108. AC & DC Input Measurement Levels .118.1 AC & DC Logic input levels for single-ended signals . 118.2 VREF Tolerances . 138.3 AC & DC Logic Input Levels for Differential Signals . 148.3.1. Differential signals definition . 148.3.2. Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS). 148.3.3. Single-ended requirements for differential signals . 158.4 Differential Input Cross Point Voltage. 178.5 Slew rate definition for Differential Input Signals . 178.6 Slew rate definitions for Differential Input Signals . 189. AC & DC Output Measurement Levels .189.1 Single-ended AC & DC Output Levels. 189.2 Differential AC & DC Output Levels. 189.3 Single-ended Output Slew Rate . 199.4 Differential Output Slew Rate . 209.5 Reference Load for AC Timing and Output Slew Rate . 209.6 Overshoot/Undershoot Specification . 219.6.1. Address and Control Overshoot and Undershoot specifications. 219.6.2. Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications . 229.7 34ohm Output Driver DC Electrical Characteristics. 239.7.1. Output Drive Temperature and Voltage Sensitivity . 259.8 On-Die Termination (ODT) Levels and I-V Characteristics. 259.8.1. ODT DC Electrical Characteristics . 269.8.2. ODT Temperature and Voltage sensitivity . 289.9 ODT Timing Definitions . 299.9.1. Test Load for ODT Timings . 299.9.2. ODT Timing Definitions . 2910. IDD Current Measure Method .3210.1 IDD Measurement Conditions . 3211. 2Gb DDR3L SDRAM F-die IDD Specification Table.4112. Input/Output Capacitance .4213. Electrical Characteristics and AC timing for DDR3-800 to DDR3-1866 .4313.1 Clock Specification . 4313.1.1. Definition for tCK(avg) . 4313.1.2. Definition for tCK(abs) . 4313.1.3. Definition for tCH(avg) and tCL(avg) . 4313.1.4. Definition for note for tJIT(per), tJIT(per, Ick) . 4313.1.5. Definition for tJIT(cc), tJIT(cc, Ick) . 4313.1.6. Definition for tERR(nper) . 4313.2 Refresh Parameters by Device Density. 4413.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin . 44-3-
K4B2G1646FdatasheetRev. 1.0DDR3L SDRAM13.3.1. Speed Bin Table Notes . 4814. Timing Parameters by Speed Grade .4914.1 Jitter Notes . 5314.2 Timing Parameter Notes. 5414.3 Address/Command Setup, Hold and Derating : . 5514.4 Data Setup, Hold and Slew Rate Derating : . 64-4-
Rev. 1.0datasheetK4B2G1646FDDR3L SDRAM1. Ordering Information[ Table 1 ] Samsung 2Gb DDR3L F-die ordering information MA96 FBGA128Mx16K4B2G1646F-BMK0K4B2G1646F-BMMA96 FBGANOTE :1. Speed bin is in order of CL-tRCD-tRP.2. 13th digit stands for below."Y" : Commercial temp"M" : Industrial temp3. Backward compatible to DDRL3-1600(11-11-11), DDR3L-1333(9-9-9)2. Key Features[ Table 2 ] 2Gb DDR3 F-die Speed 1.51.251.071nsCAS 63534nstRC(min)52.550.62549.548.7547.91ns JEDEC standard 1.35V(1.28V 1.45V) & 1.5V(1.425V 1.575V) VDDQ 1.35V(1.28V 1.45V) & 1.5V(1.425V 1.575V) 400 MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin,667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin933MHz fCK for 1866Mb/sec/pin Unit8 BanksProgrammable CAS Latency(posted CAS): 5,6,7,8,9,10,11,13Programmable Additive Latency: 0, CL-2 or CL-1 clockProgrammable CAS Write Latency (CWL) 5 (DDR3-800), 6(DDR3-1066), 7 (DDR3-1333), 8 (DDR3-1600) and 9(DDR3-1866)8-bit pre-fetchBurst Length: 8 , 4 with tCCD 4 which does not allow seamless reador write [either On the fly using A12 or MRS]Bi-directional Differential Data-StrobeInternal(self) calibration : Internal self calibration through ZQ pin(RZQ : 240 ohm 1%)On Die Termination using ODT pinAverage Refresh Period 7.8us at lower than TCASE 85 C, 3.9us at85 C TCASE 95 CThe 2Gb DDR3 SDRAM F-die is organized as a 16Mbit x 16 I/Os x 8 banksdevice. This synchronous device achieves high speed double-data-ratetransfer rates of up to 1866Mb/sec/pin (DDR3-1866) for general applications.The chip is designed to comply with the following key DDR3 SDRAM features such as posted CAS, Programmable CWL, Internal (Self) Calibration,On Die Termination using ODT pin and Asynchronous Reset .All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the crosspoint of differential clocks (CK rising and CK falling). All I/Os are synchronized with apair of bidirectional strobes (DQS and DQS) in a source synchronous fashion. The address bus is used to convey row, column, and bank addressinformation in a RAS/CAS multiplexing style. The DDR3 device operateswith a single 1.35V(1.28V 1.45V) or 1.5V(1.425V 1.575V) power supplyand 1.35V(1.28V 1.45V) or 1.5V(1.425V 1.575V) VDDQ.The 2Gb DDR3 F-die device is available in 96balls FBGA(x16). Support Industrial Temp ( -40 95 C )- tREFI 7.8us at -40 C TCASE 85 C- tREFI 3.9us at 85 C TCASE 95 C Asynchronous Reset Package : 96 balls FBGA - x16 All of Lead-Free products are compliant for RoHS All of products are Halogen-freeNOTE : 1. This data sheet is an abstract of full DDR3 specification and does not cover the common features which are described in “DDR3 SDRAM Device Operation & TimingDiagram”.2. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.-5-
Rev. 1.0datasheetK4B2G1646FDDR3L SDRAM3. Package pinout/Mechanical Dimension & Addressing3.1 x16 Package Pinout (Top view) : 96ball FBGA SRESETA13NCA8VSST1ABBall Locations (x16)CDEPopulated ballBall not populatedFGHJKTop view(See the balls through the package)LMNPRT-6-23456789
Rev. 1.0datasheetK4B2G1646FDDR3L SDRAM3.2 FBGA Package Dimension (x16)Units : Millimeters7.50 0.10 A0.80 x 8 6.40 0.809 8#A1 INDEX MARK1.603.2096 - 0.48 Solder ball(Post Reflow 0.50 0.05)13.30 0.10 0.80 x 15 12.000.400.80(Datum B)6.00ABCDEFGHJKLMNPRT(Datum A)B7 6 5 4 3 2 1(0.30)(0.60)MOLDING AREA0.2 M A B0.10MAXBOTTOM VIEW7.50 0.10 13.30 0.10 #A10.37 0.051.10 0.10TOP VIEW-7-
datasheetK4B2G1646FRev. 1.0DDR3L SDRAM4. Input/Output Functional Description[ Table 3 ] Input/Output function descriptionSymbolTypeFunctionCK, CKInputClock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing ofthe positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CKClock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers andoutput drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), orActive Power-Down (Row Active in any bank). CKE is asynchronous for self refresh exit. After VREFCA has becomeCKEInputCSInputChip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection onsystems with multiple Ranks. CS is considered part of the command code.ODTInputOn Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3 SDRAM. Whenenabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS, NU/TDQS (When TDQS is enabled via ModeRegister A11 1 in MR1) signal for x8 configurations. The ODT pin will be ignored if the Mode Register (MR1) is programmed to disable ODT.RAS, CAS, WEInputCommand Inputs: RAS, CAS and WE (along with CS) define the command being entered.DM(DMU), (DML)InputInput Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS. For x8 device, the function ofDM or TDQS/TDQS is enabled by Mode Register A11 setting in MR1.BA0 - BA2InputBank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is beingapplied. Bank address also determines if the mode register or extended mode register is to be accessed during aMRS cycle.A0 - A13InputAddress Inputs: Provided the row address for Active commands and the column address for Read/Write commandsto select one location out of the memory array in the respective bank. (A10/AP and A12/BC have additional functions,see below) The address inputs also provide the op-code during Mode Register Set commands.A10 / APInputAutoprecharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be performed to the accessed bank after the Read/Write operation. (HIGH:Autoprecharge; LOW: No Autoprecharge)A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) orall banks (A10 HIGH). if only one bank is to be precharged, the bank is selected by bank addresses.A12 / BCInputBurst Chop:A12 is sampled during Read and Write commands to determine if burst chop(on-the-fly) will be performed. (HIGH : no burst chop, LOW : burst chopped). See command truth table for detailsRESETInputActive Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when RESET is HIGH.RESET must be HIGH during normal operation. RESET is a CMOS rail to rail signal with DC high and low at 80% and20% of VDD, i.e. 1.20V for DC high and 0.30V for DC low.DQInput/OutputData Input/ Output: Bi-directional data bus.DQS, (DQS)Input/OutputData Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. For thex16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corresponds to the data on DQU0-DQU7. The datastrobe DQS, DQSL and DQSU are paired with differential signals DQS, DQSL and DQSU, respectively, to provide differential pair signaling to the system during reads and writes. DDR3 SDRAM supports differential data strobe only anddoes not support single-ended.TDQS, (TDQS)OutputTermination Data Strobe: TDQS/TDQS is applicable for X8 DRAMs only. When enabled via Mode Register A11 1 inMR1, DRAM will enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. Whendisabled via mode register A11 0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. x4/x16 DRAMs must disable the TDQS function via mode register A11 0 in MR1.NCstable during the power on and initialization sequence, it must be maintained during all operations (including SelfRefresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODTand CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during Self -Refresh.No Connect: No internal electrical connection is present.VDDQSupplyDQ Power Supply: 1.35V(1.28V 1.45V) & 1.5V(1.425V 1.575V)VSSQSupplyDQ GroundVDDSupplyPower Supply: 1.35V(1.28V 1.45V) & 1.5V(1.425V 1.575V)VSSSupplyGroundVREFDQSupplyReference voltage for DQVREFCASupplyReference voltage for CAZQSupplyReference Pin for ZQ calibrationNOTE : Input only pins (BA0-BA2, A0-A13, RAS, CAS, WE, CS, CKE, ODT and RESET) do not supply termination.-8-
Rev. 1.0datasheetK4B2G1646FDDR3L SDRAM5. DDR3 SDRAM Addressing1GbConfiguration256Mb x 4128Mb x 864Mb x 16# of Bank888Bank AddressBA0 - BA2BA0 - BA2BA0 - BA2Auto prechargeA10/APA10/APA10/APRow AddressA0 - A13A0 - A13A0 - A12Column AddressA0 - A9,A11A 0 - A9A0 - A9BC switch on the flyA12/BCA12/BCA12/BCPage size *11 KB1 KB2 KBConfiguration512Mb x 4256Mb x 8128Mb x 162Gb# of Bank888Bank AddressBA0 - BA2BA0 - BA2BA0 - BA2Auto prechargeA10/APA10/APA10/APRow AddressA0 - A14A0 - A14A0 - A13Column AddressA0 - A9,A11A 0 - A9A0 - A9BC switch on the flyA12/BCA12/BCA12/BCPage size *11 KB1 KB2 KBConfiguration1Gb x 4512Mb x 8256Mb x 16# of Bank888Bank AddressBA0 - BA2BA0 - BA2BA0 - BA2Auto prechargeA10/APA10/APA10/AP4GbRow AddressA0 - A15A0 - A15A0 - A14Column AddressA0 - A9,A11A 0 - A9A0 - A9BC switch on the flyA12/BCA12/BCA12/BC1 KB1 KB2 KBConfiguration2Gb x 41Gb x 8512Mb x 16# of Bank888Bank AddressBA0 - BA2BA0 - BA2BA0 - BA2Auto prechargeA10/APA10/APA10/APPage size*18GbRow AddressA0 - A15A0 - A15A0 - A15Column AddressA0 - A9,A11,A13A0 - A9,A11A0 - A9BC switch on the flyA12/BCA12/BCA12/BC2 KB2 KB2 KBPage size*1NOTE 1 : Page size is the number of bytes of data delivered from the array to the internal sense amplifiers when an ACTIVE command is registered.Page size is per bank, calculated as follows:page size 2 COLBITS * ORG 8where, COLBITS the number of column address bits, ORG the number of I/O (DQ) bits-9-
Rev. 1.0datasheetK4B2G1646FDDR3L SDRAM6. Absolute Maximum Ratings6.1 Absolute Maximum DC Ratings[ Table 4 ] Absolute Maximum DC RatingsSymbolParameterRatingUnitsNOTEVDDVoltage on VDD pin relative to Vss-0.4 V 1.80 VV1,3VDDQVoltage on VDDQ pin relative to Vss-0.4 V 1.80 VV1,3VIN, VOUTVoltage on any pin relative to Vss-0.4 V 1.80 VV1TSTGStorage Temperature-55 to 100 C1, 2NOTE :1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of thedevice at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditionsfor extended periods may affect reliability.2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.3. VDD and VDDQ must be within 300mV of each other at all times;and VREF must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500mV; VREF may beequal to or less than 300mV.6.2 DRAM Component Operating Temperature Range[ Table 5 ] Temperature RangeSymbolParameterTOPEROperating Temperature RangeratingUnitNOTENormal0 to 95 C1, 2, 4Industrial-40 to 95 C1, 3, 4NOTE :1. Operating Temperature TOPER is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the JEDEC documentJESD51-2.2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0-85 C under all operating conditions3. The Industrial Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between -40-85 C under all operating conditions4. Some applications require operation of the Extended Temperature Range between 85 C and 95 C case temperature. Full specifications are guaranteed in this range, but thefollowing additional conditions apply:a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us.b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to use the Manual Self-Refresh mode with Extended Temperature Rangecapability (MR2 A6 0b and MR2 A7 1b).7. AC & DC Operating Conditions7.1 Recommended DC operating Conditions[ Table 6 ] Recommended DC Operating ConditionsSymbolVDDVDDQParameterSupply VoltageSupply Voltage for OutputOperation TEV1, 2, 31.5V1.4251.51.575V1, 2, 31.35V1.2831.351.45V1, 2, 31.5V1.4251.51.575V1, 2, 3NOTE :1. Under all conditions VDDQ must be less than or equal to VDD.2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.3. VDD & VDDQ rating are determined by operation voltage.- 10 -
Rev. 1.0datasheetK4B2G1646FDDR3L SDRAM8. AC & DC Input Measurement Levels8.1 AC & DC Logic input levels for single-ended signals[ Table 7 ] Single-ended AC & DC input levels for Command and Address DDR3L-1866Max.Min.Max.UnitNOTE1.35VVIH.CA(DC90)DC input logic highVREF 90VDDVREF 90VDDmV1VIL.CA(DC90)DC input logic lowVSSVREF - 90VSSVREF - 90mV1VREF 160Note 2--mV1,2,5Note 2VREF - 160--mV1,2,5VREF 135Note 2VREF 135Note 2mV1,2,5Note 2VREF-135Note 2VREF-135mV1,2,5VIH.CA(AC125) AC input logic high--VREF 125Note 2mV1,2,5VIL.CA(AC125)--Note 2VREF CA(AC160) AC input logic highVIL.CA(AC160)AC input logic lowVIH.CA(AC135) AC input logic highVIL.CA(AC135)VREFCA(DC)AC input logic lowMAC input logic lowReference Voltage for ADD,CMD inputsNOTE : 1. For input only pins except RESET, VREF VREFCA(DC)2. See "Overshoot and Undershoot specifications" section.3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than /-1% VDD (for reference: approx. /- 13.5 mV).4. For reference: approx. VDD/2 /- 13.5 mV5. These levels apply for 1.35 Volt operation only. If the device is operated at 1.5 V , the respective levels in JESD79-3 (VIH/L.CA(DC100), VIH/L.CA(AC175), VIHL.CA(AC150),VIH/L.CA(AC135), VIH/L.CA(AC125)etc.) apply. The 1.5 V levels (VIH/L.CA(DC100), VIH/L.CA(AC175), VIH/L.CA(AC150), VIH/L.CA(AC135), VIHL.CA(AC125)etc.) do notapply when the device is operated in the 1.35 voltage range.[ Table 8 ] Single-ended AC & DC input levels for Command and )DC input logic highVREF 100VDDVREF 100VDDmV1,5VIL.CA(DC100)DC input logic lowVSSVREF - 100VSSVREF - 100mV1,6VREF 175Note 2--mV1,2,7Note 2VREF - 175--mV1,2,8VREF 150Note 2--mV1,2,7Note 2VREF-150--mV1,2,8VIH.CA(AC135) AC input logic high--VREF 135Note 2mV1,2,7VIL.CA(AC135)--Note 2VREF - 135mV1,2,8VIH.CA(AC125) AC input logic high--VREF 125Note 2mV1,2,7VIL.CA(AC125)--Note ,4,9VIH.CA(AC175) AC input logic highVIL.CA(AC175)AC input logic lowVIH.CA(AC150) AC input logic highVIL.CA(AC150)VREFCA(DC)AC input logic lowAC input logic lowAC input logic lowReference Voltage for ADD,CMD inputsNOTE : 1. For input only pins except RESET, VREF VREFCA(DC)2. See "Overshoot and Undershoot specifications" section.3. The ac peak noise on VRef may not allow VRef to deviate from VRefCA(DC) by more than /-1% VDD (for reference: approx. /- 15 mV).4. For reference: approx. VDD/2 /- 15 mV.5. VIH(dc) is used as a simplified symbol for VIH.CA(DC100)6. VIL(dc) is used as a simplified symbol for VIL.CA(DC100)7. VIH(ac) is used as a simplified symbol for VIH.CA(AC175), VIH.CA(AC150), VIH.CA(AC135), and VIH.CA(AC125); VIH.CA(AC175) value is used when Vref 0.175V isreferenced, VIH.CA(AC150) value is used when Vref 0.150V is referenced, VIH.CA(AC135) value is used when Vref 0.135V is referenced, and VIH.CA(AC125) value isused when Vref 0.125V is referenced.8. VIL(ac) is used as a simplified symbol for VIL.CA(AC175), VIL.CA(AC150), VIL.CA(AC135) and VIL.CA(AC125); VIL.CA(AC175) value is used when Vref - 0.175V isreferenced, VIL.CA(AC150) value is used when Vref - 0.150V is referenced, VIL.CA(AC135) value is used when Vref - 0.135V is referenced, and VIL.CA(AC125) value isused when Vref - 0.125V is referenced.9. VREFCA(DC) is measured relative to VDD at the same point in time on the same device- 11 -
Rev. 1.0datasheetK4B2G1646FDDR3L SDRAM[ Table 9 ] Single-ended AC & DC input levels for DQ and DM 0DDR3L-1866UnitNOTEVDDmV1VSSVREF - 90mV1---mV1,2,5----mV1,2,5Note 2VREF 135Note 2--mV1,2,5VREF - 135Note 2VREF - 135--mV1,2,5Min.Max.Min.Max.Min.Max.VIH.DQ(DC90) DC input logic highVREF 90VDDVREF 90VDDVREF 90VIL.DQ(DC90) DC input logic lowVSSVREF - 90VSSVREF - 90VIH.DQ(AC160) AC input logic highVREF 160Note 2-VIL.DQ(AC160) AC input logic lowNote 2VREF - 160VIH.DQ(AC135) AC input logic highVREF 135VIL.DQ(AC135) AC input logic lowNote 21.35VVIH.DQ(AC130) AC input logic high----VREF 130Note 2mV1,2,5VIL.DQ(AC130) AC input logic low----Note 2VREF - 0.51*VDDV3,4VREFDQ(DC)Reference Voltage for DQ,DM inputsNOTE :1. For input only pins except RESET, VREF VREFDQ(DC)2.See "Overshoot and Undershoot specifications" section.3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than /-1% VDD (for reference: approx. /- 13.5 mV).4. For reference: approx. VDD/2 /- 13.5 mV.5. These levels apply for 1.35 Volt operation only. If the device is operated at 1.5 V, the respective levels in JESD79-3 ( VIH/L.DQ(DC100), VIH/L.DQ(AC175), VIH/L.DQ(AC150), VIH/L.DQ(AC135), etc. ) apply. The 1.5 V levels (VIH/L.DQ(DC100), VIH/L.DQ(AC175), VIH/L.DQ(AC150), VIH/L.DQ(AC135), etc. ) do not apply when thedevice is operated in the 1.35 voltage range.[ Table 10 ] Single-ended AC & DC input levels for DQ and DM DC100) DC input logic highVREF 100VDDVREF 100VDDVREF 100VDDmV1,5VIL.DQ(DC100) DC input logic lowVSSVREF - 100VSSVREF - 100VSSVREF - 100mV1,6VIH.DQ(AC175) AC input logic highVREF 175NOTE 2----mV1,2,7VIL.DQ(AC175) AC input logic lowNOTE 2VREF - 175----mV1,2,8VIH.DQ(AC150) AC input logi
f vddq dql2 dqsl dql1 dql3 vssq f g vssq dql6 dqsl dd vss vssq g h vrefdq ddq dql4 dql7 dql5 vddq h j nc vss ras ck ss nc j k odt vdd cas ck dd cke k l nc cs we a10/ap zq nc l m vss ba0 ba2 nc vrefca ss m n vdd a3 a0 a12/bc ba1 dd n p vss a5 a2 a1 a4 vss p r vdd a7 a9 a11 a6 vdd r t vss reset a13 nc a8 vss t populated ball ball not populated .
PSI AP Physics 1 Name_ Multiple Choice 1. Two&sound&sources&S 1∧&S p;Hz&and250&Hz.&Whenwe& esult&is:& (A) great&&&&&(C)&The&same&&&&&
Argilla Almond&David Arrivederci&ragazzi Malle&L. Artemis&Fowl ColferD. Ascoltail&mio&cuore Pitzorno&B. ASSASSINATION Sgardoli&G. Auschwitzero&il&numero&220545 AveyD. di&mare Salgari&E. Avventurain&Egitto Pederiali&G. Avventure&di&storie AA.&VV. Baby&sitter&blues Murail&Marie]Aude Bambini&di&farina FineAnna
The program, which was designed to push sales of Goodyear Aquatred tires, was targeted at sales associates and managers at 900 company-owned stores and service centers, which were divided into two equal groups of nearly identical performance. For every 12 tires they sold, one group received cash rewards and the other received
College"Physics" Student"Solutions"Manual" Chapter"6" " 50" " 728 rev s 728 rpm 1 min 60 s 2 rad 1 rev 76.2 rad s 1 rev 2 rad , π ω π " 6.2 CENTRIPETAL ACCELERATION 18." Verify&that ntrifuge&is&about 0.50&km/s,∧&Earth&in&its& orbit is&about p;linear&speed&of&a .
theJazz&Band”∧&answer& musical&questions.&Click&on&Band .
6" syl 4" syl 12" swgl @ 45 & 5' o.c. 12" swchl 6" swl r1-1 ma-d1-6a 4" syl 4" syl 2' 2' r3-5r r4-7 r&d 14.7' 13' cw open w11-15 w16-9p ma-d1-7d 12' 2' w4-3 moonwalks abb r&d r&d r&d r&d r&d r&d ret ret r&d r&d r&d r&d r&d 12' 24' r&d ma-d1-7a ma-d1-7b ret r&d r&d r5-1 r3-2 r&d r&r(b.o.) r6-1r r3-2 m4-5 m1-1 (i-195) m1-1 (i-495) m6-2l om1-1 .
s& . o Look at the poem’s first and last lines (first and last lines may give readers important . it is important to read poems four times. Remind them that the first time they read is for enjoyment; rereads allow them to dive deeper into poems .
Andreas Wagner. ERAD 2014 - THE EIGHTH EUROPEAN CONFERENCE ON RADAR IN METEOROLOGY AND HYDROLOGY ERAD 2014 Abstract ID 306 2 Using a pattern recognition scheme, single pixels or groups of pixels that show unusual signatures compared to precipitation echoes, are identified in these accumulation products. Such signatures may be straight edges, high gradients or systematic over- or .
