Zynq UltraScale MPSoC Data Sheet: DC And AC Switching .
Zynq UltraScale MPSoC Data Sheet:DC and AC Switching CharacteristicsDS925 (v1.3) April 20, 2017Preliminary Product SpecificationSummaryThe Xilinx Zynq UltraScale MPSoCs are available in -3, -2, -1 speed grades, with -3E devices havingthe highest performance. The -2LE and -1LI devices can operate at a V CCINT voltage at 0.85V or 0.72V andare screened for lower maximum static power. When operated at V CCINT 0.85V, using -2LE and -1LIdevices, the speed specification for the L devices is the same as the -2I or -1I speed grades. Whenoperated at VCCINT 0.72V, the -2LE and -1LI performance and static and dynamic power is reduced.DC and AC characteristics are specified in extended (E) and industrial (I) temperature ranges. Except theoperating temperature range or unless otherwise noted, all the DC and AC electrical parameters are thesame for a particular speed grade (that is, the timing characteristics of a -1 speed grade extended deviceare the same as for a -1 speed grade industrial device). However, only selected speed grades and/ordevices are available in each temperature range.All supply voltage and junction temperature specifications are representative of worst-case conditions.The parameters included are common to popular designs and typical applications.This data sheet, part of an overall set of documentation on the Zynq UltraScale MPSoCs, is available onthe Xilinx website at www.xilinx.com/documentation.DC CharacteristicsAbsolute Maximum RatingsTable 1: Absolute Maximum Ratings(1)SymbolDescriptionMinMaxUnitsProcessor System (PS)VCC PSINTFPPS primary logic full-power domain supply voltage.–0.5001.000VVCC PSINTLPPS primary logic low-power domain supply voltage.–0.5001.000VVCC PSAUXPS auxiliary supply voltage.–0.5002.000VVCC PSINTFP DDRPS DDR controller and PHY supply voltage.–0.5001.000VVCC PSADCPS SYSMON ADC supply voltage relative to GND PSADC.–0.5002.000VVCC PSPLLPS PLL supply voltage.–0.5001.320VVPS MGTRAVCCPS-GTR supply voltage.–0.5001.000VVPS MGTRAVTTPS-GTR termination voltage.–0.5002.000VVPS MGTREFCLKPS-GTR reference clock input voltage.–0.5001.100VVPS MGTRINPS-GTR receiver input voltage.–0.5001.100V Copyright 2015–2017 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks ofXilinx in the United States and other countries. AMBA, AMBA Designer, ARM, ARM1176JZ-S, CoreSight, Cortex, and PrimeCell are trademarks of ARM in the EU and othercountries. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their respective owners.DS925 (v1.3) April 20, 2017Preliminary Product Specificationwww.xilinx.comSend Feedback1
Zynq UltraScale MPSoC Data Sheet: DC and AC Switching CharacteristicsTable 1: Absolute Maximum Ratings(1) (Cont’d)SymbolDescriptionMinMaxUnitsVCCO PSDDRPS DDR I/O supply voltage.–0.5001.650VVCC PSDDR PLLPS DDR PLL supply voltage.–0.5002.000VVCCO PSIOPS I/O supply.–0.5003.630VPS I/O input voltage.–0.500VCCO PSIO 0.550VPS DDR I/O input voltage.–0.500VCCO PSDDR 0.550VPS battery-backed RAM and battery-backed real-timeclock (RTC) supply voltage.–0.5002.000VInternal supply voltage.–0.5001.000VInternal supply voltage for the I/O banks.–0.5001.000VVCCAUXAuxiliary supply voltage.–0.5002.000VVCCBRAMSupply voltage for the block RAM memories.–0.5001.000VOutput drivers supply voltage for HD I/O banks.–0.5003.400VVPSIN(2)VCC PSBATTProgrammable Logic (PL)VCCINTVCCINT IO(3)VCCOOutput drivers supply voltage for HP I/O banks.–0.5002.000VVCCAUX IO(4)Auxiliary supply voltage for the I/O banks.–0.5002.000VVREFInput reference voltage.–0.5002.000V–0.550VCCO 0.550VI/O input voltage for HP I/O banks.–0.550VCCO 0.550VIDCAvailable output current at the pad.–2020mAIRMSAvailable RMS output current at the pad.–2020mAVIN(2)(5)(7)I/O input voltage for HD I/Obanks.(6)GTH or GTY TransceiverVMGTAVCCAnalog supply voltage for transceiver circuits.–0.5001.000VVMGTAVTTAnalog supply voltage for transceiver ary analog Quad PLL (QPLL) voltage supply r reference clock absolute input voltage.–0.5001.300VVMGTAVTTRCALAnalog supply voltage for the resistor calibration circuitof the transceiver column.–0.5001.300VVINReceiver (RXP/RXN) and transmitter (TXP/TXN) absoluteinput voltage.–0.5001.200VIDCIN-FLOATDC input current for receiver input pins DC coupled RXtermination floating.(8)–10mAIDCIN-MGTAVTTDC input current for receiver input pins DC coupled RXtermination VMGTAVTT.–10mAIDCIN-GNDDC input current for receiver input pins DC coupled RXtermination GND.(9)–0mAIDCIN-PROGDC input current for receiver input pins DC coupled RXtermination programmable.(10)–0mAIDCOUT-FLOATDC output current for transmitter pins DC coupled RXtermination floating.–6mAIDCOUT-MGTAVTTDC output current for transmitter pins DC coupled RXtermination VMGTAVTT.–6mADS925 (v1.3) April 20, 2017Preliminary Product Specificationwww.xilinx.comSend Feedback2
Zynq UltraScale MPSoC Data Sheet: DC and AC Switching CharacteristicsTable 1: Absolute Maximum Ratings(1) 0VVideo Codec UnitVCCINT VCUInternal supply voltage for the video codec unit.PL System MonitorVCCADCPL System Monitor supply relative to GNDADC.0.5002.000VVREFPPL System Monitor reference input relative to GNDADC.0.5002.000V–65150 CTemperatureTSTGStorage temperature (ambient).TSOLMaximum soldering temperature.(12)–260 CTjMaximum junction temperature.(12)–125 CNotes:1.Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These arestress ratings only, and functional operation of the device at these or any other conditions beyond those listed underOperating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time mightaffect device reliability.2. When operating outside of the recommended operating conditions, refer to Table 6, Table 7, and Table 8 for maximumovershoot and undershoot specifications.3. VCCINT IO must be connected to VCCBRAM.4. VCCAUX IO must be connected to VCCAUX.5. The lower absolute voltage specification always applies.6. If VCCO is 3.3V, the maximum voltage is 3.4V.7. For I/O operation, see the UltraScale Architecture SelectIO Resources User Guide (UG571).8. AC coupled operation is not supported for RX termination floating.9. For GTY transceivers, DC coupled operation is not supported for RX termination GND.10. DC coupled operation is not supported for RX termination programmable.11. For more information on supported GTH or GTY transceiver terminations see the UltraScale Architecture GTH TransceiverUser Guide (UG576) or UltraScale Architecture GTY Transceiver User Guide (UG578).12. For soldering guidelines and thermal considerations, see the Zynq UltraScale MPSoC Packaging and Pinout Specifications(UG1075).DS925 (v1.3) April 20, 2017Preliminary Product Specificationwww.xilinx.comSend Feedback3
Zynq UltraScale MPSoC Data Sheet: DC and AC Switching CharacteristicsRecommended Operating ConditionsTable 2: Recommended Operating Conditions(1)(2)SymbolDescriptionMinTypMaxUnitsPS full-power domain supply voltage.0.8080.8500.892VFor -1LI and -2LE (VCCINT 0.72V) devices:PS full-power domain supply voltage.0.8080.8500.892VFor -3E devices:PS full-power domain supply voltage.0.8730.9000.927VPS low-power domain supply voltage.0.8080.8500.892VFor -1LI and -2LE (VCCINT 0.72V) devices:PS low-power domain supply voltage.0.8080.8500.892VFor -3E devices:PS low-power domain supply voltage.0.8730.9000.927VPS auxiliary supply voltage.1.7101.8001.890VPS DDR controller and PHY supply voltage.0.8080.8500.892V0.8080.8500.892VFor -3E devices:PS DDR controller and PHY supply voltage.0.8730.9000.927VVCC PSADCPS SYSMON ADC supply voltage relative toGND PSADC.1.7101.8001.890VVCC PSPLLPS PLL supply voltage.1.1641.2001.236VVPS MGTRAVCCPS-GTR supply voltage.0.8250.8500.875VVPS MGTRAVTTPS-GTR termination voltage.1.7461.8001.854VVCCO PSDDR(4)PS DDR I/O supply voltage.1.06–1.575VVCC PSDDR PLLPS DDR PLL supply voltage.1.7101.8001.890VVCCO PSIO(5)PS I/O supply.1.710–3.465VPS I/O input voltage.–0.200–VCCO PSIO 0.200VPS DDR I/O input voltage.–0.200–VCCO PSDDR 0.2001.200–1.500VPL internal supply voltage.0.8250.8500.876VFor -1LI and -2LE (VCCINT 0.72V) devices:PL internal supply voltage.0.6980.7200.742VFor -3E devices: PL internal supply voltage.0.8730.9000.927VPL internal supply voltage for the I/O banks.0.8250.8500.876VFor -1LI and -2LE (VCCINT 0.72V) devices:PL internal supply voltage for the I/O banks.0.8250.8500.876VFor -3E devices: PL internal supply voltage for the I/Obanks.0.8730.9000.927VBlock RAM supply voltage.0.8250.8500.876VFor -3E devices: block RAM supply voltage.0.8730.9000.927VAuxiliary supply voltage.1.7461.8001.854VProcessor SystemVCC PSINTFP(3)VCC PSINTLPVCC PSAUXFor -1LI and -2LE (VCCINT 0.72V) devices:VCC PSINTFP DDR(3) PS DDR controller and PHY supply voltage.VPSINVCC PSBATT(6)PS battery-backed RAM and battery-backed real-timeclock (RTC) supply voltage.Programmable LogicVCCINTVCCINT IO(7)VCCBRAMVCCAUXDS925 (v1.3) April 20, 2017Preliminary Product Specificationwww.xilinx.comSend Feedback4
Zynq UltraScale MPSoC Data Sheet: DC and AC Switching CharacteristicsTable 2: Recommended Operating Conditions(1)(2) (Cont’d)SymbolVCCO(8)VCCAUX IO(9)VIN(10)IIN(11)DescriptionMinTypMaxUnitsSupply voltage for HD I/O banks.1.140–3.400VSupply voltage for HP I/O banks.0.950–1.900VAuxiliary I/O supply voltage.1.7461.8001.854V–0.200–VCCO 0.200V––10mAI/O input voltage.Maximum current through any PL or PS pin in apowered or unpowered bank when forward biasing theclamp diode.GTH or GTY TransceiverVMGTAVCC(12)Analog supply voltage for the GTH or GTY transceiver.0.8730.9000.927VVMGTAVTT(12)Analog supply voltage for the GTH or GTY transmitterand receiver termination circuits.1.1641.2001.236VVMGTVCCAUX(12)Auxiliary analog QPLL voltage supply for alog supply voltage for the resistor calibrationcircuit of the GTH or GTY transceiver column.1.1641.2001.236VInternal supply voltage for the VCU.0.8250.8500.876VFor -1LI and -2LE (VCCINT 0.72V) devices:Internal supply voltage for the VCU.0.8250.8500.876VFor -3E devices: Internal supply voltage for the VCU.0.8730.9000.927VVCUVCCINT VCUDS925 (v1.3) April 20, 2017Preliminary Product Specificationwww.xilinx.comSend Feedback5
Zynq UltraScale MPSoC Data Sheet: DC and AC Switching CharacteristicsTable 2: Recommended Operating Conditions(1)(2) (Cont’d)SymbolDescriptionMinTypMaxUnitsPL System MonitorVCCADCPL System Monitor supply relative to GNDADC.1.7461.8001.854VVREFPPL System Monitor externally supplied referencevoltage relative to GNDADC.1.2001.2501.300VJunction temperature operating range for extended (E)temperature devices.(14)0–100 CJunction temperature operating range for industrial (I)temperature devices.–40–100 CJunction temperature operating range for eFUSEprogramming.–40–125 .13.14.All voltages are relative to GND.For the design of the power distribution system consult UltraScale Architecture PCB Design Guide (UG583).VCC PSINTFP DDR must be tied to VCC PSINTFP.Includes VCCO PSDDR of 1.2V, 1.35V, 1.5V at 5% and 1.1V 0.07V/–0.04V depending upon the tolerances required byspecific memory standards.Applies to all PS I/O supply banks. Includes VCCO PSIO of 1.8V, 2.5V, and 3.3V at 5%.If the battery-backed RAM or RTC is not used, connect VCC PSBATT to GND or VCC PSAUX. The VCC PSAUX maximum of 1.89Vis acceptable on an unused VCC PSBATT.VCCINT IO must be connected to VCCBRAM.Includes VCCO of 1.0V (HP I/O only), 1.2V, 1.35V, 1.5V, 1.8V, 2.5V (HD I/O only) at 5%, and 3.3V (HD I/O only) at 3/–5%.VCCAUX IO must be connected to VCCAUX.The lower absolute voltage specification always applies.A total of 200 mA per bank should not be exceeded.Each voltage listed requires filtering as described in UltraScale Architecture GTH Transceiver User Guide (UG576) orUltraScale Architecture GTY Transceiver User Guide (UG578).Xilinx recommends measuring the Tj of a device using the system monitor as described in the UltraScale ArchitectureSystem Monitor User Guide (UG580). The SYSMON temperature measurement errors (that are described in Table 69 andTable 124) must be accounted for in your design. For example, when using the PL system monitor with an externalreference of 1.25V, when SYSMON reports 97 C, there is a measurement error 3 C. A reading of 97 C is considered themaximum adjusted Tj (100 C – 3 C 97 C).Devices labeled with the speed/temperature grade of -2LE normally operate under Extended (E) temperature gradespecifications with a maximum junction temperature of 100 C. However, E temperature grade devices can operate for alimited time at a junction temperature of 110 C. Timing parameters adhere to the same speed file at 110 C as they do at100 C, regardless of operating voltage (nominal voltage of 0.85V or a low-voltage of 0.72V). Operation at Tj 110 C islimited to 1% of the device lifetime and can occur sequentially or at regular intervals as long as the total time does notexceed 1% of the device lifetime.DS925 (v1.3) April 20, 2017Preliminary Product Specificationwww.xilinx.comSend Feedback6
Zynq UltraScale MPSoC Data Sheet: DC and AC Switching CharacteristicsAvailable Speed Grades and Operating VoltagesTable 3 describes the speed grades per device and the V CCINT operating supply voltages for the full-power,low-power, and DDR domains. For more information on selecting devices and speed grades, see theUltraScale Architecture and Product Overview (DS890).Table 3: Available Speed Grades and Operating VoltagesSpeed GradeVCCINTVCC PSINTLPVCC PSINTFPVCC PSINTFP -2LE0.720.850.850.85V-1LI0.720.850.850.85VDC Characteristics Over Recommended Operating ConditionsTable 4: DC Characteristics Over Recommended Operating Data retention VCCINT voltage (below which configurationdata might be lost).0.68––VVDRAUXData retention VCCAUX voltage (below which configurationdata might be lost).1.5––VIREFVREF leakage current per pin.––15µA––15µADie input capacitance at the pad (HP I/O).––3.1pFDie input capacitance at the pad (HD I/O).––4.75pFPad pull-up (when selected) at VIN 0V, VCCO 3.3V.75–190µAPad pull-up (when selected) at VIN 0V, VCCO 2.5V.50–169µAPad pull-up (when selected) at VIN 0V, VCCO 1.8V.60–120µAPad pull-up (when selected) at VIN 0V, VCCO 1.5V.30–120µAPad pull-up (when selected) at VIN 0V, VCCO 1.2V.10–100µAPad pull-down (when selected) at VIN 3.3V.60–200µAPad pull-down (when selected) at VIN 1.8V.29–120µAILCIN(3)IRPUIRPDInput or output leakage current per pin(sample-tested).(2)ICCADCONPLAnalog supply current for the PL SYSMON circuits in thepower-up state.––8mAICCADCONPSAnalog supply current for the PS SYSMON circuits in thepower-up state.––10mAICCADCOFFPLAnalog supply current for the PL SYSMON circuits in thepower-down state.––1.5mAICCADCOFFPSAnalog supply current for the PS SYSMON circuits in thepower-down state.––1.8mADS925 (v1.3) April 20, 2017Preliminary Product Specificationwww.xilinx.comSend Feedback7
Zynq UltraScale MPSoC Data Sheet: DC and AC Switching CharacteristicsTable 4: DC Characteristics Over Recommended Operating Conditions (Cont’d)SymbolICC ttery supply current at VCC PSBATT 1.50V, RTC enabled.––3650nABattery supply current at VCC PSBATT 1.50V, RTC disabled.––650nABattery supply current at VCC PSBATT 1.20V, RTC enabled.––3150nABattery supply current at VCC PSBATT 1.20V, RTC disabled.––150nAPS VCC PSAUX additional supply current during eFUSEprogramming.––115mACalibrated programmable on-die termination (DCI) in HP I/O banks(8) (measured per JEDEC specification)R(9)Thevenin equivalent resistance of programmable inputtermination to VCCO/2 where ODT RTT 40.–10%(7)40 10%(7)ΩThevenin equivalent resistance of programmable inputtermination to VCCO/2 where ODT RTT 48.–10%(7)48 10%(7)ΩThevenin equivalent resistance of programmable inputtermination to VCCO/2 where ODT RTT 60.–10%(7)60 10%(7)ΩProgrammable input termination to VCCO whereODT RTT 40.–10%(7)40 10%(7)ΩProgrammable input termination to VCCO whereODT RTT 48.–10%(7)48 10%(7)ΩProgrammable input termination to VCCO whereODT RTT 60.–10%(7)60 10%(7)ΩProgrammable input termination to VCCO whereODT RTT 120.–10%(7)120 10%(7)ΩProgrammable input termination to VCCO whereODT RTT 240.–10%(7)240 10%(7)ΩUncalibrated programmable on-die termination in HP I/Os banks (measured per JEDEC specification)R(9)Thevenin equivalent resistance of programmable inputtermination to VCCO/2 where ODT RTT 40.–50%40 50%ΩThevenin equivalent resistance of programmable inputtermination to VCCO/2 where ODT RTT 48.–50%48 50%ΩThevenin equivalent resistance of programmable inputtermination to VCCO/2 where ODT RTT 60.–50%60 50%ΩProgrammable input termination to VCCO whereODT RTT 40.–50%40 50%ΩProgrammable input termination to VCCO whereODT RTT 48.–50%48 50%ΩProgrammable input termination to VCCO whereODT RTT 60.–50%60 50%ΩProgrammable input termination to VCCO whereODT RTT 120.–50%120 50%ΩProgrammable input termination to VCCO whereODT RTT 240.–50%240 50%ΩUncalibrated programmable on-die termination in HD I/O banks (measured per JEDEC specification)R(9)Thevenin equivalent resistance of programmable inputtermination to VCCO/2 where ODT RTT 48.–50%48 50%Ω50% VCCOVCCO x0.49VCCO x0.50VCCO x0.51V70% VCCOVCCO x0.69VCCO x0.70VCCO x0.71VInternal VREFDS925 (v1.3) April 20, 2017Preliminary Product Specificationwww.xilinx.comSend Feedback8
Zynq UltraScale MPSoC Data Sheet: DC and AC Switching CharacteristicsTable 4: DC Characteristics Over Recommended Operating Conditions 100 35%ΩDifferentialterminationProgrammable differential termination (TERM 100)for HP I/O banks.nTemperature diode ideality factor.–1.026––rTemperature diode series l values are specified at nominal voltage, 25 C.For HP I/O banks with a VCCO of 1.8V and separated VCCO and VCCAUX IO power supplies, the IL maximum current is 70 µA.This measurement represents the die capacitance at the pad, not including the package.Maximum value specified for worst case process at 25 C.ICC PSBATT is measured when the battery-backed RAM (BBRAM) is enabled.Do not program eFUSE during device configuration (e.g., during configuration, during configuration readback, or whenreadback CRC is active).If VRP resides at a different bank (DCI cascade), the range increases to 15%.VRP resistor tolerance is (240Ω 1%)On-die input termination resistance, for more information see the UltraScale Architecture SelectIO Resources User Guide(UG571).Table 5: PS MIO Pull-up and Pull-down CurrentSymbolIRPUIRPDDescriptionMinMaxUnitsPad pull-up (when selected) at VIN 0V, VCCO PSMIO 3.3V.2080µAPad pull-up (when selected) at VIN 0V, VCCO PSMIO 2.5V.2080µAPad pull-up (when selected) at VIN 0V, VCCO PSMIO 1.8V.1565µAPad pull-down (when selected) at VIN 3.3V.2080µAPad pull-down (when selected) at VIN 2.5V.2080µAPad pull-down (when selected) at VIN 1.8V.1565µADS925 (v1.3) April 20, 2017Preliminary Product Specificationwww.xilinx.comSend Feedback9
Zynq UltraScale MPSoC Data Sheet: DC and AC Switching CharacteristicsVIN Maximum Allowed AC Voltage Overshoot and UndershootTable 6: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HD I/O Banks(1)AC Voltage Overshoot % of UI at –40 C to 100 C AC Voltage Undershoot % of UI at –40 C to 100 CVCCO 0.30100%–0.30100%VCCO 0.35100%–0.3590%VCCO 0.40100%–0.4078%VCCO 0.45100%–0.4540%VCCO 0.50100%–0.5024%VCCO 0.55100%–0.5518.0%VCCO 0.60100%–0.6013.0%VCCO 0.65100%–0.6510.8%VCCO 0.7092%–0.709.0%VCCO 0.7592%–0.757.0%VCCO 0.8092%–0.806.0%VCCO 0.8592%–0.855.0%VCCO 0.9092%–0.904.0%VCCO 0.9592%–0.952.5%Notes:1.A total of 200 mA per bank should not be exceeded.Table 7: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HP I/O Banks(1)(2)AC Voltage Overshoot % of UI at –40 C to 100 C AC Voltage Undershoot % of UI at –40 C to 100 CVCCO 0.30100%–0.30100%VCCO 0.35100%–0.35100%VCCO 0.4092%–0.4092%VCCO 0.4550%–0.4550%VCCO 0.5020%–0.5020%VCCO 0.5510%–0.5510%VCCO 0.606%–0.606%VCCO 0.652%–0.652%VCCO 0.702%–0.702%Notes:1.2.A total of 200 mA per bank should not be exceeded.For UI smaller than 20 µs.DS925 (v1.3) April 20, 2017Preliminary Product Specificationwww.xilinx.comSend Feedback10
Zynq UltraScale MPSoC Data Sheet: DC and AC Switching CharacteristicsTable 8: VPSIN Maximum Allowed AC Voltage Overshoot and Undershoot for PS I/O Banks(1)AC Voltage Overshoot % of UI at –40 C to 100 C AC Voltage Undershoot % of UI at –40 C to 100 CVCCO PSIO 0.30100%–0.30100%VCCO PSIO 0.35100%–0.3575%VCCO PSIO 0.40100%–0.4045%VCCO PSIO 0.45100%–0.4540%VCCO PSIO 0.5075%–0.5010%VCCO PSIO 0.5575%–0.556%VCCO PSIO 0.6060%–0.602%VCCO PSIO 0.6530%–0.650%VCCO PSIO 0.7020%–0.700%VCCO PSIO 0.7510%–0.750%VCCO PSIO 0.8010%–0.800%VCCO PSIO 0.858%–0.850%VCCO PSIO 0.906%–0.900%VCCO PSIO 0.956%–0.950%Notes:1.A total of 200 mA per bank should not be exceeded.DS925 (v1.3) April 20, 2017Preliminary Product Specificationwww.xilinx.comSend Feedback11
Zynq UltraScale MPSoC Data Sheet: DC and AC Switching CharacteristicsQuiescent Supply CurrentTable 9: Typical Quiescent Supply Current(1)(2)(3)(4)SymbolICCINTQICCINT IOQICCOQICCAUXQDescriptionQuiescent VCCINT supply current.Quiescent VCCINT IO supply current.Quiescent VCCO supply current.Quiescent VCCAUX supply current.DS925 (v1.3) April 20, 2017Preliminary Product SpecificationDeviceSpeed Grade andVCCINT Operating 396396396396396mAAll deviceswww.xilinx.comSend Feedback12
Zynq UltraScale MPSoC Data Sheet: DC and AC Switching CharacteristicsTable 9: Typical Quiescent Supply Current(1)(2)(3)(4) (Cont’d)SymbolICCAUX IOQICCBRAMQDescriptionQuiescent VCCAUX IO supply current.Quiescent VCCBRAM supply current.DeviceSpeed Grade andVCCINT Operating 3535mANotes:1.2.3.4.Typical values are specified at nominal voltage, 85 C junction temperatures (Tj) with single-ended SelectIO resources.Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pinsare 3-state and floating.Use the Xilinx Power Estimator (XPE) spreadsheet tool (download at www.xilinx.com/power) to estimate static powerconsumption for conditions or supplies other than those specified.Typical values depend upon your configuration. To accurately estimate all PS supply currents, use the interactive XPEspreadsheet tool.DS925 (v1.3) April 20, 2017Preliminary Product Specificationwww.xilinx.comSend Feedback13
Zynq UltraScale MPSoC Data Sheet: DC and AC Switching CharacteristicsPower Supply SequencingPS Power-On/Off Power Supply SequencingThe low-power domain (LPD) must operate before the full-power domain (FPD) can function. Thelow-power and full-power domains can be powered simultaneously. The PS POR B input must be assertedto GND during the power-on sequence (see Table 37). The FPD (when used) must be powered beforePS POR B is released.To achieve minimum current draw and ensure that the I/Os are 3-stated at power-on, the recommendedpower-on sequence for the low-power domain (LPD) is listed. The recommended power-off sequence isthe reverse of the power-on sequence.1. VCC PSINTLP2. VCC PSAUX, VCC PSADC, and VCC PSPLL in any order or simultaneously.3. VCCO PSIOTo achieve minimum current draw and ensure that the I/Os are 3-stated at power-on, the recommendedpower-on sequence for the full-power domain (FPD) is listed. The recommended power-off sequence isthe reverse of the power-on sequence.1. VCC PSINTFP and V CC PSINTFP DDR driven from the same supply source.2. VPS MGTRAVCC and VCC PSDDR PLL in any order or simultaneously.3. VPS MGTRAVTT and VCCO PSDDR in any order or simultaneously.PL Power-On/Off Power Supply SequencingThe recommended power-on sequence is VCCINT , VCCINT IO/VCCBRAM/VCCINT VCU, VCCAUX/VCCAUX IO, andVCCO to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. Therecommended power-off sequence is the reverse of the power-on sequence. If VCCINT andVCCINT IO/VCCBRAM have the same recommended voltage levels, they can be powered by the same supplyand ramped simultaneously. V CCINT IO must be connected to VCCBRAM. If VCCAUX/VCCAUX IO and V CCO havethe same recommended voltage levels, they can be powered by the same supply and rampedsimultaneously. V CCAUX and VCCAUX IO must be connected together. VCCADC and VREF can be powered atany time and have no power-up sequencing requirements.The recommended power-on sequence to achieve minimum current draw for the GTH or GTY transceiversis V CCINT, VMGTAVCC, V MGTAVTT OR V MGTAVCC, VCCINT, VMGTAVTT. There is no recommended sequencing forVMGTVCCAUX. Both VMGTAVCC and VCCINT can be ramped simultaneously. The recommended power-offsequence is the reverse of the power-on sequence to achieve minimum current draw.If these recommended sequences are not met, current drawn from V MGTAVTT can be higher thanspecifications during power-up and power-down.DS925 (v1.3) April 20, 2017Preliminary Product Specificationwww.xilinx.comSend Feedback14
Zynq UltraScale MPSoC Data Sheet: DC and AC Switching CharacteristicsPS-PL Power SequencingThe PS and PL power supplies are fully independent. All PS power supplies can be powered before or afterany PL power supplies. The PS and PL power regions are isolated to prevent damage.Power Supply RequirementsTable 10 shows the minimum current, in addition to ICCQ maximum, required by each Zynq UltraScale device for proper power-on and configuration. If the current minimums shown in Table 10 are met, thedevice powers on after all supplies have passed through their power-on reset threshold voltages. Thedevice must not be configured until after VCCINT is applied. Once initialized and configured, use the XilinxPower Estimator (XPE) tools to estimate current drain on these supplies.Table 10: Power-on Current by Device(1)ICC Min ICCQ ICCINTQ ICCINTMINICCINT IOMIN ICCBRAMQ ICCBRAMMINICCINT IOQ ICCOMINICCOQ ICCAUXMIN ICCAUX IOMINICCAUXQ ICCAUX IOQ XCZU2 XCZU3 XCZU4 XCZU5 XCZU6 XCZU7 XCZU9 XCZU11 XCZU15 XCZU17 XCZU19 :1.Use the Xilinx Power Estimator (XPE) spreadsheet tool (download at www.xilinx.com/power) to estimate power-on currentfor all supplies.Table 11 shows the power supply ramp time.Table 11: Power Supply Ramp TimeSymbolDescriptionMinMaxUnitsTVCCINTRamp time from GND to 95% of VCCINT.0.240msTVCCINT IORamp time from GND to 95% of VCCINT IO.0.240msTVCCINT VCURamp time from GND to 95% of VCCINT VCU.0.240msTVCCORamp time from GND to 95% of VCCO.0.240msTVCCAUXRamp time from GND to 95% of VCCAUX.0.240msTVCCBRAMRamp time from GND to 95% of VCCBRAM.0.240msTMGTAVCCRamp time from GND to 95% of VMGTAVCC.0.240msTMGTAVTTRamp time from GND to 95% of VMGTAVTT.0.240msTMGTVCCAUXRamp time from GND to 95% of VMGTVCCAUX.0.240msTVCC PSINTFPRamp time from GND to 95% of VCC PSINTFP.0.240msTVCC PSINTLPRamp time from GND to 95% of VCC PSINTLP.0.240msTVCC PSAUXRamp time from GND to 95% of VCC PSAUX.0.240msTVCC PSINTFP DDRRamp time from GND to 95% of VCC PSINTFP DDR.0.240msTVCC PSADCRamp time from GND to 95% of VCC PSADC.0.240msTVCC PSPLLRamp time from GND to 95% of VCC PSPLL.0.240msTPS MGTRAVCCRamp time from GND to 95% of VCC MGTRAVCC.0.240msTPS MGTRAVTTRamp time from GND to 95% of VCC MGTRAVTT.0.240msDS925 (v1.3) April 20, 2017Preliminary Product Specificationwww.xilinx.comSend Feedback15
Zynq UltraScale MPSoC Data Sheet: DC and AC Switching CharacteristicsTable 11: Power Supply Ramp Time (Cont’d)SymbolDescriptionMinMaxUnitsTVCCO PSDDRRamp time from GND to 95% of VCCO PSDDR.0.240msTVCC PSDDR PLLRamp time from GND to 95% of VCC PSDDR PLL.0.240msTVCCO PSIORamp time from GND to 95% of VCCO PSIO.0.240msDC Input and Output LevelsValues for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over therecommended operating conditions at the VOL and V OH test points. Only selected standards are tested.These are chosen to ensure that all standards meet their specifications. The selected standards are testedat a minimum V CCO with the respective VOL and VOH voltage levels shown. Other standards are sam
VCC_PSINTFP_DDR(3) PS DDR controller and PHY supply voltage. 0.808 0.850 0.892 V For -1LI and -2LE (VCCINT 0.72V) devices: PS DDR controller and PHY supply voltage. 0.808 0.850 0.892 V For -3E devices: PS DDR controller and PHY supply voltage. 0.873 0.900 0.927 V VCC_PSADC PS SYSMON ADC
Zynq UltraScale MPSoC: Embedded Design Tutorial 9 UG1209 (v2019.2) October 30, 2019 www.xilinx.com Chapter 1:Introduction Other Vivado Components Other Vivado components include: Embedded/Soft IP for the Xilinx embedded processors Documentation Sample projects PetaLinux Tools The PetaLinux tools set is an Embedded Linux System .
UltraScale Architecture Memory Resources 7 UG573 (v1.12) March 17, 2021 www.xilinx.com Chapter 1: Block RAM Resources Zynq UltraScale MPSoC devices provide 64-bit processor scalability while combining real-
Zynq Migration Guide 6 UG1213 (v3.0) November 22, 2019 www.xilinx.com Chapter 1:Introduction Video codec unit (VCU): Simultaneous Encode and Decode through separate cores H.264 high profile level 5.2 (4Kx2K-60) H.265 (HEVC) main, main10 profile, level 5.1, high Tier, up to 4Kx2K-60 rate 8-bit and 10-bit encoding 4:2:0 and 4:2:2 chroma sampling
Zynq-7000 SoC Data Sheet: Overview DS190 (v1.11.1) July 2, 2018 www.xilinx.com Product Specification 5 Zynq-7000 Family Description The Zynq-7000 family offers the flexibility and scalability of an F
configurable wrapper to allow the RF-DAC and RF-ADC blocks to be used in IP integrator designs. IMPORTANT! In this guide reference is made to the Dual and Quad RF-ADC and RF-DAC tiles; for the actual sampling rate specifications, see the Zynq UltraScale RFSoC Data Sheet: DC and AC Switching Characteristics (DS926).
configurable wrapper to allow the RF-DAC and RF-ADC blocks to be used in IP integrator designs. IMPORTANT! In this guide reference is made to the Dual and Quad RF-ADC and RF-DAC tiles; for the actual sampling rate specifications, see the Zynq UltraScale RFSoC Data Sheet: DC and AC Switching Characteristics (DS926).
UltraScale Architecture CLB User Guide www.xilinx.com 5 UG574 (v1.5) February 28, 2017 Chapter 1 Overview Introduction to UltraScale Architecture The Xilinx UltraScale architecture is a revo lutionary approach to creating programmable devices capable of addressing the massive I/O and memory bandwidth requirements of
UltraScale Architecture and Product Data Sheet: Overview DS890 (v4.0) March 16, 2021 www.xilinx.com Product Specification 4 Configuration, Encryption, and System Monitoring The configuration and encryption block performs numerous device-level functions critical to the successful operation of the FPGA, MPSoC, or RFSoC.
